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Why no more 100 pin design?

Blog Post created by linyan on Oct 15, 2015

Why no more 100pin (Banshee) design

 

 

1.           The crystals and load capacitors that are specified on Banshee(100 pin design) do not meet the gain margin specifications recommended by ST.  As a result, the external 32.768kHz and 25.0MHz oscillators (LSE and HSE respectively) may not start up reliably.

 

2.           The TI TPS7A4501 LDO regulator was discovered to have low phase margin (~20deg) which can cause ringing on the 4V RF supply during a transient load change. Power engineer would like to see 45deg to 60deg of phase margin to avoid potential oscillations under temperature and tolerance variations. TI has confirmed this issue using their own evaluation board and can reproduce the behavior that we're seeing on the Cisco boards.  End result is TPS7A4501 is NOT recommended for use with the reference design.

 

3. R23, R86 should be BOM=NONE

 

4. We changed Y2 to Epson TG-5021CG-39N 38.88MHz TCXO because the 40MHz TCXO was causing ~6dB desense on channel 44.

 

5. Recommend changing SKY65313 VPC voltage divider to 1k/2.2k instead of 10k/22k (R93/R99) if it doesn't negatively impact the outage lifetime on their device.  This is because of feedback from one of the RF engineers "The impedance of the VPC pin changes when transmitting and the higher resistance divider lets the VPC pin voltage move around.  We found the power rise time changed and when you look at the VPC voltage versus time and the tx power versus time there was variation when using the 10k/22k resistors. After changing to the 1k/2.2k resistors, the VPC voltage is well behaved.  During rfdvt over temp we found the change was required."

 

 

 

 

 

 

 

More detail on #1:

 

 

 

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Nneed to verify that your crystals meet the following requirements (I can’t tell from the spreadsheet what the p/n are):

 

 

 

a) Verify the choice of crystal and load caps meet the requirements specified in the AN2867 Oscillator Design Guide. Gm is 5 mA/V for the HSE and 2.8 μA/V for LSE.

 

 

 

From the guide:

 

 

 

    "A gain margin of 5 can be considered as a minimum to ensure an efficient startup of oscillations."

 

 

 

b) Verify the choice of crystal and load caps meet the following requirements specified in section 5.3.8 of the STM32 datasheet:

 

 

 

High Speed Oscillator (25.0MHz):

 

 

 

    "For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 29). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2."

 

 

 

Low Speed Oscillator (32.768KHz):

 

 

 

    "For CL1 and CL2 it is recommended to use high-quality external ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 30). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.

 

 

 

    Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF.

 

 

 

    To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL <= 7 pF. Never use a resonator with a load capacitance of 12.5 pF."

 

 

 

Recommended components:

 

 

 

Our initial testing has shown that the following crystal and load capacitor pairs provide good results (the CL values are dependent upon PCB capacitance Cstray and should be tuned based upon the actual board layout).

 

32.768kHz:

 

 

 

    Epson MC-306 32.7680K-E:PURE SN (CPN 19-1373-02)

 

    CL=4.7pF: Kemet C0402C479D5GAC (CPN 11-1795-02)

 

 

 

25.0MHz:

 

 

 

    Epson TSX-3225-25.000MF20X-AJ (CPN 19-2514-01)

 

    CL=8.2pF: Murata GRM1555C1H8R2DA01 (CPN 11-1990-02)

 

 

 

More detail on #2

 

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The TI recommended TPS7A4501 LDO regulator was discovered to have low phase margin (~20deg) which can cause ringing on the 4.0V RF rail during a transient load change. Power engineer would like to see 45deg to 60deg of phase margin to avoid potential oscillations under temperature and tolerance variations. TI has confirmed this issue using their own evaluation board and can reproduce the behavior that we're seeing on the Cisco boards.  TI recommends replacing with TPS7A8300 (not pin-compatible).  TI has also tested TPS78601 at 4.3V output with a 22uF 6.3V output capacitor and 75k/30.1k feedback resistors. TI had to add a 22pF feed-forward capacitor across the top feedback resistor in order to provide enough phase margin for stability. Your PCB doesn’t have the footprint for the feed forward capacitor on the layout. 

 

 

 

 

 

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